1. Field of the Invention
The invention relates to the field of design methodologies for electrical circuits, in particular digital circuits for use in mixed signal systems and thus comprising digital and analog parts, as well as circuits designed in accordance with the methodologies. More particularly, the invention relates to a method for minimizing the influence of a first digital sub-circuit on an at least partially digital circuit, the first digital sub-circuit being part of the at least partially digital circuit, to a second digital sub-circuit adapted for minimizing the influence of the first digital sub-circuit, to the at least partially digital circuit and to an at least partially digital circuit comprising such a second digital sub-circuit.
2. Description of the Related Technology
Digital switching noise that propagates through a chip substrate and/or through power/ground rails to an analog circuitry on a same chip is a major limitation for mixed-signal System-on-Chip (SoC) integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce.
With the increase of switching speed of digital circuits and tighter signal-to-noise ratio specifications in analog circuits, ground bounce is a stopper for single-chip integration of mixed-signal systems [‘D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, Vol. 28, No. 4, pp. 420-430, 1993 and M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee’ and ‘B. A. Wooley, “Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver,” IEEE J. of Solid-State Circuits, Vol. 36, No. 3, pp. 473-485, 2001’]. Even if for a mixed-signal application, the analog part is put on a separate die than the digital part, the data converters are usually put on the same chip as the digital part, where they are subject to noise coupling, which is mainly caused by ground bounce in the digital domain.
A technique called spread spectrum clock generation (SSCG) was introduced in ‘K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in IEEE Proc. of the Int. Symp. on Electromagnetic Compatibility, pp. 227-231, August 1994’ to reduce the spectral peaks of the digital clock as much as 10-20 dB by frequency modulation of the clock with a unique waveform. Through this modulation, the energy at each clock harmonic is distributed over a wider bandwidth. For the case of a 266 MHz clock with a triangular modulation and with a 2.5% frequency deviation, around 13 dB attenuation is measured with this technique [H.-H. Chang, I.-H. Hua, and S.-L. Liu, “A spread-spectrum clock generator with triangular modulation,” IEEE J. Solid-State Circuits, Vol. 38, No. 4, April 2003].
Previous work has focused more on a single cell with a single-cycle input and ignored the impact of the system-level clocking on the ground bounce [T. Gabara, W. Fischer, J. Harrington, and W. W. Troutman, “Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers,” IEEE J. Solid-State Circuits, Vol. 32, No. 3, pp. 407-418, 1997].
Introducing intended skews to the synchronous clock network in order to spread the simultaneous switching activities as such is known from ‘M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. Gielen, and H. De Man, “Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits,” IEEE J. Solid-State Circuits, Vol. 37, No. 11, pp. 1383-1395, November 2002’.